This invention relates to methods for testing semiconductor chips. Semiconductor chips are typically manufactured on wafers, with several chips being fabricated on a single wafer. After the wafers are fabricated, they are first probed, then sawn into individual chips. The chips are then packaged and tested. If the test indicates a chip to be defective, the chip and package are discarded.
A problem with this testing and shipping procedure is that attaching the chip to the package is an expensive process; in addition, the chip package itself may be expensive. The probing step prevents some defective chips from being packaged, but probe testing is not satisfactory, because some defects are introduced in later steps, such as sawing or when the chip is packaged. Additionally, the chips cannot be tested "at speed," that is, under the conditions they will eventually be used, because the electrical connection between the test probe and the chip is inadequate for high speed testing.
Thus, a method for testing chips which allows the chip to be tested in its package, but which allows defective chips to be easily removed from the package in a manner that allows the package to be reused, is desirable.
Two related methods for forming temporary bonds are described in U.S. Pat. No. 4,804,132, issued Feb. 14, 1989 to DiFrancesco and U.S. Pat. No. 5,083,697 issued Jan. 28, 1992, also to DiFrancesco. In the methods disclosed in the DiFrancesco patents, a method for establishing electrical contacts of two surfaces in which one of the surfaces has metallized particles that protrude at the desired bonding point. The strength of the bond can be controlled by varying the size of the particles and the piercing depth.
For the methods disclosed in the DiFrancesco patents to work for chip testing, the piercing depth of the metallized particles must be precisely controlled. Insufficient piercing depth can mean that the electrical contact is insufficient for accurate testing, and excessive piercing depth can result in a bond being made unintentionally permanent, or damaging the contact pad or the underlying substrate. A semiconductor chip typically may have several hundred contact pads. The height of the contact pads may vary, and the semiconductor substrate may be slightly non-planar, which makes keeping the piercing depth for each of the pads within the desired range difficult. Additionally, the chip must be precisely aligned with the contact pads to allow "at speed" electrical testing. Thus, there is an additional need to align the chip to the pads in the test package.